1. Field of the Invention
The present invention relates to integrated circuit design optimization and in particular to generating net routing constraints for place and route, thereby improving pre-route and post-route correlation. This improved correlation results in better resource efficiency and quicker design closure.
2. Related Art
As technology nodes for integrated circuits get smaller, different parts of the design may pose significant challenges for IC designers. For example, wire delays can dominate cell delays in designs that use process technologies at 65 nm and below. Wire delay mis-correlation can be due to routing topologies, such as high fanout or congested areas of the design. Further, delay caused by via resistance can become an important issue for the 28 nm technology node and below. Currently, it is difficult to predict how many vias and what kind of vias will be used early in the design development. Yet further, lower metal layers can have 20-40 times per unit length resistance compared to higher metal layers at the 28 nm technology node and below. As a result, long nets in upper layers can have pessimistic delay estimations, and short nets in lower layers can have optimistic delay estimations.
A conventional place and route tool performs virtual (rough) routing based on an initial placement for net pins (stage referenced as “pre-route” herein). To address the above-described delay estimation issues, the conventional place and route tool uses average values for wire delays, via counts, and layer resistances. In contrast, during actual routing (stage also referenced as “post-route” herein), the conventional place and route tool uses detailed wire delays, via counts, and layer resistances, thereby generating quite accurate delay estimations. Unfortunately, to generate these delay estimations, significant system and time resources are needed. Therefore, to ensure the user is provided quick feedback on the design, virtual routing continues to use a less accurate delay model during the pre-route stage.
As a result of the above-described issues, the delay of a net assumed during circuit optimization at the pre-route stage may be very different from its actual delay after routing, thereby consequently misdirecting circuit optimization. This misdirecting may also leave critical nets un-optimized or non-critical nets over-optimized during pre-route optimization.
Therefore, a need arises for a method of improving pre-route and post-route delay correlation to provide an optimized circuit design. Because pre-route optimization is significantly more flexible than post-route optimization, post-route optimization should use limited optimization tricks to fix timing and design rule violations that cannot be easily predicted at the pre-route stage for design closure.